SEI 1618

Phase Locked Loop

The SEI-1618PG is a Phase Lock Loop (PLL) chip designed to provide frequency control in a PLL at fractional multiples of the reference frequency. Its fractional design provides improved phase noise in phase lock systems within the loop bandwidth and gives a greater flexibility than any other fractional chip on the market.

The device’s fractionality can be programmed to be any value from 1/1 to 1/64. To form a complete PLL, only a VCO, an external loop filter, and dual modulus prescaler are required. The use of an external prescaler allows the designer the flexibility of choosing one with the most appropriate divide ratios.

• Operating Instructions for SEI-1618PG Fractional Phase Lock Loop (The SEI-1618EB evaluation card was designed to demonstrate ALL™ (fractional) technology. The ALL™ is a patented fractional PLL circuit, and is fully programmable — i.e., both the counters and the fractionality.
  
  
• Operating Instructions for SEI-1618EB-00 Technology Evaluation Kit